1. Field of the Invention
This invention is related to the field of conditional clock buffer circuits.
2. Description of the Related Art
As electronic circuits increase in density, particularly integrated circuits, power consumption has also increased. In order to minimize power consumption, power management circuitry may be used. Power management circuitry may be used to selectively and/or temporarily remove power from a certain part of an electronic circuit during times while that part is inactive. Alternatively or in addition, conditional clocking schemes may be used.
Conditional clocking may be used to conditionally generate a clock to a functional circuit dependent on whether or not the functional circuit is active. If the circuit is active, the clock is generated (e.g. rising and falling edges are generated providing a high phase and a low phase of the clock signal). If the circuit is inactive, the clock may be inhibited (e.g. held in a constant state instead of toggling high and low). Inhibiting the clock during idle times for the functional circuit may result in power savings since the state of the circuit is held steady and thus the circuit may experience minimal switching activity. Typically, the condition input to the conditional clock circuitry (which determines whether the clock is generated or inhibited) has a relatively high setup time and/or hold time with regard to an input clock edge, to ensure glitch free operation of the conditional clock.
For example, an AND gate may be used to generate a conditional clock (with one input being the input clock and the other being the condition signal, indicating when high that the output clock is to toggle). In this case, the setup time for the condition signal may be relatively short, but the hold time may be approximately one half clock cycle (since the condition signal is required to remain valid, either high or low, throughout the high phase of the input clock). As another example, an AND gate with a passgate latch on the condition signal input may be used. While the hold time may be shorter than the single AND gate (e.g. approximately the hold time of the passgate latch), the setup time is lengthened since the conditional signal must propagate through the passgate latch prior to the rising edge of the input clock.
A conditional clock buffer circuit includes a clock output and is coupled to receive a clock input and a condition signal. The conditional clock buffer circuit includes a first circuit coupled to receive the clock input and a second circuit coupled to receive the clock input and the condition signal. The first circuit is configured to generate a first state on the clock output responsive to a first phase of the clock input. The second circuit is configured to conditionally generate a second state on the clock output responsive to the condition signal during a first portion of a second phase of the clock input. In some embodiments, a latch circuit may be coupled to the first and second circuits and to the clock output, and the latch circuit may be configured to hold the state of the clock output during the remaining portion of the second phase of the clock input. The setup and hold times for the condition signal may be relative to the first portion of the second phase, and may, in some embodiments, be relatively short. In one implementation, one or more of the conditional clock buffer circuits may be included in a clock tree. The clock tree may also include one or more levels of buffering coupled to receive an input clock and output a buffered clock. The clock input of the conditional clock buffers may be coupled to the buffer clock.